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january 2015 ? 20 11 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus fsa9285a mcpc-compliant, usb-port, multimedia switch with auto-detection, 12 v v bus features switch type audio, fs/ hs -usb, charging switch mechanism programmable switching with available interrupt accessory detection headsets with mic and send/end usb data cable usb chargers (car, cdp, dcp) usb on-the-go (otg) mcpc specification compliant programmable m odes usb fs and hs 2.0 compliant usb charging battery charging 1.2 compliant integrated fet, charger detect, ocp (1.45 a), ovp (6.5 v - 14 .0 v) audio left, right, mic (negative swing) built-in termination resistors for audio pop reduction v bat 2.7 to 4.4 v programmability i 2 c esd 15 kv iec 61000-4-2 air gap package 20 -lead, wl csp (2.010 x 1.672 x 0.625 mm , 0.4 mm pitch) ordering information FSA9285AUCX description the fsa9285a is a high-performance multimedia switc h featuring automatic switching and accessory detecti on for a usb port. the fsa9285a allows sharing of a common usb p ort to pass audio and usb data while simultaneously chargi ng. in addition, the fsa9285a integrates detection of accessories such as headphones, headsets mobile computing promotion consortium (mcpc) with mic and send/end, car chargers, usb chargers, usb on -the-go (otg), and accessory charging adapters (aca) to use a common usb connector. the fsa9285a can be programmed for manual or automatic switching of usb data paths based on the accessory detected . with an integrated 14 v over-voltage and 1.45 a over-current protected fet, the fsa9285a integrates common usb protection functions for v bus . applications ? mobile phones, portable media players
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 2 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus block diagram figure 1. block diagram pin configuration figure 2. pin assignments (top-through view) vbus_in vbat vddio intb vbus_out dm_con dm_host2 i2c_sda i2c_scl audio_l dp_con dp_host2 mic chg_detb audio_r id_con gnd gnd1 dm_host1 dp_host1 ab c d e 1 2 3 4 hs - usb baseband processor v bus_in dm_con dp_con gnd id_con intb i2c_scl i2c_sda v ddio dp_host1 dm_host1 i 2 c audio_r audio_l dp_host2 dm_host2 interrupt fsa9285a mic float / short detect charger detect switch control and i 2 c slave 3:1 mux and charge pump v bat resistance detection chg_detb v bus_out usb port dm_con dp_con gnd id_con audio codec hs - usb charger ic phone power detection ocp, ovp v bus_in
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 3 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus pin descriptions name pin # type default state description usb interface dp_host1 d1 signal path open d+ signal switch path, dedicated usb port to be connected to the resident usb transceiver on the phone dm_host1 c1 signal path open d- signal switch path , dedicated usb port to be connected to the resident usb transceiver on the phone dp_host2 a2 signal path open d+ signal switch path, dedicated usb port to be connected to the resident usb transceiver on the phone dm_host2 a3 signal path open d- signal switch path , dedicated usb port to be connected to the resident usb transceiver on the phone v bus_in e4 power path n/a input voltage supply pin to be connected to the v bus pin of the usb connector v bus_out d4 power path n/a output voltage supply pin to be connected to the source volta ge pin on the charger ic chg_detb c2 open-drain output hi -z open-drain active low output, used to signal the charger ic that a charger has been attached audio interface audio_r d2 signal path open right audio channel switch path from mobile phone audio codec audio_l d3 signal path open left audio channel switch path from mobile phone audio codec mic b2 signal path open connected to the mobile phone audio codec mic input pin to complete the mic switch path connector interface id_con e1 signal path open connected to the usb connector id pin and used for detecting accessories or button presses dp_con e2 signal path open connected to the usb connector d+ pin ; d epending on the signaling mode, can be switched to dp_host1 , dp_host2, or audio _r pins dm_con e3 signal path open connected to the usb connector d- pin ; d epending on the signaling mode, can switched to dm_host1, dm_host2, or audio_l pins power interface v bat a4 power path n/a input voltage supply pin to be connected to the mobile phone batter y output or to an internal regulator on the phone v ddio b4 power path n/a baseband processor interface i/o supply pin gnd1 b1 ground n/a ground gnd a1 ground n/a ground i 2 c interface i2c_scl c3 input hi -z i 2 c serial clock signal to be connected to the phone-based i 2 c master i2c_sda b3 open-drain i/o hi -z i 2 c serial data signal to be connected to the phone-based i 2 c master intb c4 cmos output high interrupt active low output used to prompt the phone baseband processor to read the i 2 c register bits, indicates a change in id _con or v bus_in pin status or accessories attach status
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 4 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 1. functional description the fsa9285a is a usb port accessory-detection switch with integrated 14 v over-voltage and 1.45 a over-current protected fet. fully controlled using i 2 c protocols , the fsa9285a enables all of the following to use a common connector (mi cro / mini usb 2.0 port): high-speed usb 2.0 standard downstream data port, stereo and mono audio headphones / headsets wi th or without a microphone, wired remote controller with optional send / end button, usb charging downstream port (cdp) battery charger, usb dedicated charging port (dcp) charger, and ansi/cea-936-a usb car kit charger. the fsa9285a enables factory-mode testing by defaulting to manual mode (en_man_sw = 1) and defaulting the manual sw register to usb switches dp_host1 / dm_host1 closed and the v bus fet closed. in manual configuration, usb switches dp_host1 / dm_host1 only close when an accessory is attached that has an id_con resistance (id_con not floating) and / or valid v bus voltage is present. the v bus fet only closes when v bus is valid. all switches remain open to protect the system when there is no accessory attached. th is default switch condition can be overridden with i 2 c commands. detection of usb accessories utilizing a usb micro-b or micro- a/b connector is made possible by the presence of a standard re sistor between the id pin and ground of the accessory. advanced modes manage wired remote-control sensing for audio accessories. the fsa9285a is designed to allow au dio signals to swing below ground on the usb 2.0 port data lines . internal power for the fsa9285a is automatically derived from either the battery voltage (v bat ) or the usb supply (v bus_in ) for simplicity and long battery life. 2. i 2 c and digital core the fsa9285a includes a full i 2 c slave controller. the i 2 c slave fully complies with version 2. 1 of the i 2 c specification s. this block is designed for fast-mode, 400 khz signals. t he slave addresses are shown in table 1 . this block also includes the chip master controller. the chip controller monitors commands sent to the fsa9285a via i 2 c from the baseband processor and takes action. the digital core takes inputs from the various functional blocks and the i 2 c commands received from the mobile phone baseband processor and relays rele vant status updates to the phone. table 1. i 2 c slave address name size (bits) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 slave address 8 0 1 0 0 1 0 1 read / write examples of i 2 c write and read sequences are shown in figure 3 and figure 4, res pectively. figure 3. i 2 c write sequence figure 4. i 2 c read sequence from master to slave s start condition na not acknowledge (sda high) rd read =1 from slave to master a acknowledge (sda low) wr write=0 p stop condition s wr a a s rd a a a na p register address to read specified note: 8bits if register is not specified, master begins reading from current regist er. in this case, only red bracketed sequence is needed. single- or multi byte read executed from current register location (single-byte read is initiated by master with na immediately following first data byte) read data k+1 read data k+n-1 8bits 8bits 8bits slave address register address k read data k slave address s wr a a a a a a p note: single byte read is initiated by master with p immediately following first data byte. 8bits 8bits 8bits write data k+2 slave address register address k write data write data k+1 write data k+n- 1
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 5 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 3. power-up initialization and reset fsa9285a operates correctly without special power sequencing. when power is first applied, the device und ergoes a hardware reset and all the registers are initialized to the default values shown in table 6. all of the combinations of v alid v bus _ in and v bat are shown in table 2. as shown in table 2, v bat is used as the primary power supply. v ddio is the dedicated baseband io voltage and is only used for i 2 c interface and interrupt processing within the fsa9285a. when v bat is not valid, but v bus_in is; the fsa9285a powers off v bus_in . in this condition, the fsa9285a operates in its default state and is able to detect usb accessories and all chargers. t he fsa9285a always turns on the v bus fet upon any attach state with v bus _v alid (unless manual mode is enabled with the v bus fet switch state configured open). this allows charging of a dead battery when the rest of the system is not powered to configure the fsa9285a . when the device is reset, all i 2 c registers are initialized to the default values shown in table 6 (s ee section 4 - configuration) . after reset or power up, the fsa9285a enters standby mode and is ready to detect accessories sensed on its v bus_in or id_con pins. the device has three hardware reset mechanisms: ? power-on reset caused by the initial rising edge of v bus (if v bat < 1.0 v) or rising edge of v bat ( if not v bus_valid ) ? the falling edge of v ddio ? i 2 c reset: holding i2c_sda and i2c_scl low for 30 ms the device has one software reset mechanism: ? writing the resetb bit (bit 6) in the control register (02h) table 2. power states summary notes: 1. v ddio is expected to be the same supply used by the baseband i/os. 2. this is not a typical state. both v bat and v ddio are typically provided from the same regulator. 4. configuration the fsa9285a must be configured for operation upon reset. there are several options to note about reset configuration: 1. the interrupt mask bit is set and must be cleared for the fsa9285a to interrupt the host processor. 2. upon hardware reset, the usb path dp_host1 / dm_host1 switches are configured to close when an accessory is attached (with an id_con resistance or valid v bu s voltage) to support production programming. these switches may be opened using i 2 c commands. 3. if mic mode is going to be used, it is recommended that mic_ovp_en bit be set to 1 at reset. 4. to enable manual configuration of the usb switches, the en_man_sw bit must be set to 1. the switch settings then override any automatic settings (this assumes that the usb discovery state machine has completed its operations and a device is attached). for the weak (or dead) battery case to work reliably, v ddio must be removed (to reset the fsa9285a state) whenever the battery is too low for reliable i 2 c communication. 5. performing a software reset sets all i 2 c register map (table 6) registers to default, with the exception of the control register, manual sw register, and the manual chg_ctrl register. these registers are only reset to default on a hardware reset. valid v bus_in valid v bat valid v ddio (1) power state enabled functionality charging through fet processor communication (i 2 c & interrupts) detection no no no power down no no no no no yes (2) illegal state no yes no powered o ff v bat no no yes no yes yes powered o ff v bat no yes yes yes no no powered o ff v bus_in yes no yes yes yes no powered o ff v bat yes no yes yes no yes (2) powered o ff v bus_in yes yes yes yes yes yes powered o ff v ba t yes yes yes
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 6 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 5. interrupt operation the baseband processor recognizes interrupt signals by observing the intb signal, which is active low. interrupts are masked upon reset via the int mask register bit (bit 0 of control register, address 02h in table 6 of the i 2 c register map) and intb pin defaults high. after the int mask bit is cleared by the baseband processor, the intb pin is generally driven high (intb is not an open-drain output) in preparation f or a future interrupt. the intb remains high until the intb mask is cleared. if the interrupt mask bit in the i 2 c control register is written low when an interruptible event occurs, intb transitions low and returns high when the processor reads the interrupt register at addresses 03h. 6. analog switch descriptions the fsa9285a has a three-port data switch, providing routi ng capability to two data ports and one audio port. the two d ata switches are high bandwidth to provide high-speed usb 2.0 eye compliance. these switches also operate full-swing for full-speed usb and uart signals up to 4.4 v. the hi gh -performance negative-swing-capable audio switch utilizes a termination resistor for audio pop reduction. the audio configuration also provides for routing a microphone signal from a headset. the mic signals can be routed to either the v bus_in pin for stereo audio configurations or the dp_con pin for mono audio configurations that also allow simultaneous chargin g over the v bus line . 7. accessory detection in standby mode, after power-up or reset, the fsa9285a monitors the v bus_in and id_con pins for any connectivity using very low power ( see battery supply standby mode current in the switch path dc electrical characteristics section) . to minimize standby power, many functional blocks are powered down until an accessory attach is detected. the v bus_in detection recognizes if the voltage on v bus_in is within the valid range (>4.0 v) . for resistance to gnd on the id_con pin, the fsa9285a measures voltage with an injected current to determine this resistance. all accessories attached or detached are reported to the processor via the interrupt register. any changes of resistance on the id_con pin are reported as a resistor_change interrupt. additional information about the accessory is reported in the device type, resistor code, and status registers. for usb accessories without an id_con resistance, a v bu s_valid change interrupt is reported to sign al an attach or detach condition. status of v bus_valid and id_con resistance is always available after any interrupt. the usb detection flow is show in figure 5. note that the intb mask bit in the control register must be cleared after a reset or power-up before interrupts can be signaled by the fsa9285a . individual interrupt masks bits can be enabled by writing the interrupt mask register (see table 6) . id_con resistor detection is accomplished in a little more tha n three times the resistor detection time, where resistor detection time bits are programmable in the timing set register. the fsa9285a is designed to allow up to 1 nf capacitance on the id_con pin. id_con is short-circuit protected from a faulty resistor or an accidental short where the current is limited to 5 ma sourced by the fsa9285a. the detection of a v bus_in goes through the usb detection flow only once. v bus_in must be removed before the usb detection state machine reverts to its initial state. after an initial attach, the fsa9285a continuously monitors t he id pin for changes and reports those changes to the baseban d processor. to provide the fastest response for changes in button checking after initial attach, the fsa9285a indicates a change in id_con resistor after two samples are taken instead of the three consecutive samples taken on initial attach. to save power, the resistor detection block can be disabled aft er an initial attach with the id _dis bit in the control register. the resistor detection block is normally disabled when no id_ con resistance is present (id_con floating) to save power. the condition of id_float continues to be monitored regardless o f the id_dis setting. whenever a resistance is measured on id_con, the usb discovery state machine halts after completion of its curre nt state and the id_con state machine continues for accessory detection. the on ly exception is when an aca rid-a accessory is detected. in this case, the usb discovery state machine i s used to differentiate between a docking station and a powe red a-device attached to a docking station (per usb battery charging specification 1.2) . if the en_man_sw bit is set on attach, fsa9285a configures the switches to the state in the manual sw register. upon the removal of any accessory, the fsa9285a detects and indicates a change in id_con resistance (regardless of id_dis bit setting), a removal of v bus_in , or both. the fsa9285a automatically opens all switches (and v bus fet) on detach (id_float and v bus not valid), even if the fsa9285a is set to m anual switching m ode. for the weak battery case, the fsa9285a needs to be in automatic switching mode. should the processor not be able to respond to intb, fsa9285a must be placed in automatic switching mode explicitly or v ddio must be removed, resetting the fsa9285a state to its default values. note: if the fsa9285a is to be used in automatic switching mode (en_man_sw = 0) then the manual sw register must be configured for all switches open).
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 7 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus figure 5. accessory discovery state machine flow diagram note: 3. figure 5 illustrates operation with a valid v ddio supply voltage. figure 5 does not illustrate dead battery provision (dbp) see section 9 for details . v bus valid ? id = rid _ a ? charger ? dcp cdp sdp aca _ a dock car kit 1 / 2 aca _ b aca _ c other id float ? dp / dm shorted ? charger ? check v bus perform dcd check id adc change yes yes no yes yes no no no yes no no id = 200 k / 442 k ? ? id = aca rid - b id = aca rid - c yes v bus and id detection state machines operate in parallel
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 8 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus table 3. id_con resistor identification resistor code (4) id_con resistance to gnd auto switch usb switches unit accessory detected min. typ. max. 10110 0 18 ? otg 10100 19000 20000 21000 ? resistor 20 k 10011 22800 24000 25200 ? resistor 24 k 10010 27265 28700 30135 ? resistor 28.7 k 10001 34675 36500 3 6865 yes ? aca rid-c (5) 10000 39798 40200 40602 ? resistor 40.2 k 0 1111 44650 47000 49350 ? mcpc send/end 0 1110 55638 56200 56762 ? resistor 56.2 k 0 1101 64600 68000 71400 yes ? aca rid-b (5) 0 1100 80275 84500 88725 ? resistor 84.5 k ? 0 1011 96900 102000 107100 ? phone power device 0 1010 117800 124000 130200 yes ? aca rid-a (5) 0 1001 148500 150000 151500 ? resistor 150 k 0 1000 171000 180000 1836 00 ? mcpc maintenance 00111 19 8000 200000 2 02 000 ? car kit type- 1 charger (5) 00110 229680 232000 234320 ? resistor 232 k 00101 272650 287000 301350 ? mcpc mode 1 00100 370500 390000 401700 ? mcpc reserved 00011 4 3758 0 442000 4 4642 0 ? car kit type-2 charger (5) 00010 529150 557000 584850 ? mcpc mode 3 0000 1 757150 797000 836850 ? mcpc mode 2 0000 0 970000 open ? float (6) notes: 4. the resistor code values are reported in the resistor code reg ister whenever a valid resistor code value changes. 5. see table 4 for details, additional requirements may be applica ble for detection . 6. resistance ?? 970 k status bit /id_float=0.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 9 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 8. usb port and charger detection the fsa9285a can detect the usb 2.0 port type s summarized in table 4. v bus must be present to detect these accessories. for sdp, cdp, and aca usb accessories; the following pin mapping is automatically configured: ? dp_host1 = dp_con (if en_man_sw = 0) ? dm_host1 = dm_con (if en_man_sw = 0) ? v bus_out = v bus_in the fsa9285a allows factory testing or programming through the dp_host1 and dm_host1 switches by closing these switches when a usb cable with an id resistance or v bus voltage is detected. for usb chargers that do not automatically close usb switches, the switches can be closed manually through the manual switch register when en_man_sw is enabled. whenever v bus_in becomes valid, the integrated charger fet is closed (unless en_man_sw = 1 and manual sw[1:0]11) and v bus_in voltage is continuously monitored to incorporate over-voltage protection (ovp). if the attached device is recognized as one of the chargers in table 4 (excluding sdp), the chg_detb pin goes low to send a signal to the charger ic, external to the fsa9285a, to increase the charging current to the maximum allowed level by the over-current protection (ocp) trigger (see the switch path dc electrical characteristics section) . v bus_out must be valid 10 ms before sourcing greater than 100 ma. table 4. id_con and v bus detection for usb and car kit devices resistor code (7) v bus_in usb switches (8) chg_detb (8) id_con resistance to gnd accessory detected min. typ. max. 00111 5 v o pen asserted 198 k 200 k 202 k car kit type-1 charger 00011 5 v o pen asserted 437.58 k 442 k 446.42 k car kit type-2 charger 00000 5 v o pen asserted 3 m open open usb dedicated charging port, travel adapter or dedicated charger (dcp) (9) 00000 5 v auto_close asserted 3 m open open usb charging downstream port (cdp) (9) 00000 5 v auto_close not asserted 3 m open open usb standard downstream port (sdp) (9) 10001 5 v auto_close asserted 34.675 k 36.5 k 36.865 k aca rid-c 01101 5 v auto_close asserted 64.6 k 68 k 71.4 k aca rid-b 0101 0 5 v auto_close asserted 117.8 k 124 k 130.2 k aca rid-a notes: 7. the resistor code values are reported in the resistor code regis ter, independent of the state of usb switches or v bus_in . 8. in table 4, switches auto-close and chg_detb are asserted only if v bus_valid . 9. the fsa9285a follows the battery charging 1.2 specification, whic h uses dp_con and dm_con to determine the usb accessory attached. refer to battery charging 1.2 specification for details. 9. dead battery provision since v bus charging power connects through it , the fsa9285a must automatically turn on the v bus fet to allow the mobile device to charge after shutdown due to a dead battery. whe n detecting that v bus is valid, the fsa9285a automatically turns on the v bus fet after bc1.2 charger detection is complete. turning on at this time allows the dp / dm switches to turn on at the same time as the v bus fet. if the fsa9285a detects a usb port (sdp, cdp, or dcp) when v bat and v ddio are not valid, it applies 0.6 v to dp_con in accordance with the usb bc1.2 dead battery provision. the fsa9285a automatically removes the 0.6 v on dp_con upo n detach of an accessory, when v ddio returns to a valid voltage , or when v bat > v bat_th . if the mobile device should manually assert the 0.6 v on dp_con, it can do so using the assert_d+ bit (bit 2) of the manual chg_ctrl register (14h); v bus must be valid to do so.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 10 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 10. over-voltage protection (ovp) and over-current protection (ocp) when v bus_in is less than nominally 6.5 v, the fsa9285a allows the v bus_in supply to enter the chip-power select voltage regulator block. for v bus_in greater than nominally 6.5 v, the input is disconnected, protecting the fsa9285a from excess voltage. upon entering shutdown mode, the ovp bit in the interrupt register is set high (to reflect a change in ovp state) and an interrupt is sent to the baseband. the ovp status register is also written high to indicate that an ovp conditio n is present. in shutdown mode, the fsa9285a continually monitors v bus and exits shutdown mode when v bus drops to below 6.5 v or it senses an accessory detach. upon exitin g an ovp condition, another ovp interrupt is triggered (reflecting a change in ovp state) and the ovp status bit is cleared (indicating an ovp condition is not present). the over-current protection (ocp) feature limits current through the charger fet to nominally 1. 45 a. ocp is only implemented when v bus_in is provided by the attached accessory. the fsa9285a senses an over-current event, opens (turns off) the v bus fet, and reports this to the baseband by asserting the ocp bit (to reflect a change in ocp state) in the interrupt register. when in an ocp state, the ocp status bit is written high. while the ocp condition is present , the fsa9285a continually monitors the v bus current and exits shutdown mode when the v bus current drops below nominally 1. 45 a or it senses an accessory detach. upon exiting ocp st ate, the ocp interrupt bit is again written high, indicating a change in ocp state and the ocp status bit is written lo w , indicating an ocp state is not present. 11. audio accessory detection after an audio device is attached and a change in id_con resistance is detected (if id _dis=0), the fsa9285a asserts an interrupt and the baseband processor can read the resistor code register to determine the id_con resistance change to detect if a key, such as mcpc send / end , was pressed. for powered audio accessories with v bus present, the fsa9285a detects when v bus is valid and interrupts the baseband processor. the baseband processor must manua lly control the fsa9285a switches for proper functionality. mic can be switched to either v bus or dp_con through the manual sw register, allowing more flexibility.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 11 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 12. absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may a ffect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v bat /v ddio supply voltage from battery / baseband -0.5 6.0 v v bus_in supply voltage from micro-usb connector -0.5 28.0 v v sw switch i/o voltage usb -1.0 6.0 v stereo/mono audio path active -2.0 6.0 all other channels -0.5 6.0 i ik input clamp diode current - 50 ma i chg charger detect chg_detb pin current sink capability 30 ma i sw switch i/o current (continuous) usb 50 ma audio 60 all other channels 50 i swpeak peak switch current (pulsed at 1 ms duration, <10% duty cycle) usb 150 ma audio 150 ma charger fet 2 a all other channels 150 ma t stg storage temperature range - 65 +150 ? c t j maximum junction temperature +150 ? c t l lead temperature (soldering, 10 seconds) +260 ? c esd iec 61000-4-2 system level usb connector pins (dp_con, dm_con, v bus_in , id_con) to gnd air gap 15000 v contact 8000 human body model, jedec jesd22-a114 all pins 50 00 charged device model, jedec jesd22-c101 all pins 1 500 13. recommended operating conditions the recommended operating conditions table defines the con ditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommen d exceedin g them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v bat battery supply voltage 2.7 3.8 4.4 v v bat_th battery supply voltage threshold for w eak / d ead battery 2.7 3.0 3.3 v v bus_ in supply voltage from v bus_in pin 4.0 14 .0 ( 10 ) v v ddio processor supply voltage 1. 7 3.6 v v sw switch i/o voltage usb path active 0 4.4 v audio path active -1.5 3.0 all other pins 0 5.0 id cap capacitive load on id_con pin for reliable accessory detection 1.0 nf t a operating temperature - 40 +85 oc note: 10. maximum operating condition set by design.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 12 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 14. switch path dc electrical characteristics all typical values are at t a =25c unless otherwise specified. symbol parameter v bat (v) condition t a = -40 to +85c unit min. typ. max. host interface pins (intb, chg-detb) v oh output high voltage ( 11 ) 3.0 to 4.4 i oh =2 ma 0.7 x v ddio v v ol output low voltage 3.0 to 4.4 i ol =8 ma 0.4 v i 2 c interface pins C fast mode (i2c_sda, i2c_scl) v il low -level input voltage 3.0 to 4.4 0.3 x v ddio v v ih high-level input voltage 3.0 to 4.4 0.7 x v ddio v i i2c input current of i2c_sda and i2c_scl pins, input voltage 0.26 v to 2.34 v 3.0 to 4.4 - 10 10 a switch o ff characteristics i off power-off leakage current 0 all data ports except audio & mic , v sw =4.4 v 10 a i no(off) off leakage current 4.4 all ports except audio & mic , i/o pins=0.3 v, 4.1 v, or floating -0.100 0.001 0.100 a i idshrt short-circuit current 3.0 to 4.4 current limit if id_con=0 5 ma usb switch (dp_hostn, dm_hostn) on paths r on usb switch paths on resistance ( 12 , 13 ) 3.0 to 4.4 v d+/d- =0, 0.4 v, i on =8 ma 8 10 ? v d+/d- =0, 3.6 v, i on =8 ma 11 17 ? charging fet on path v ovp over-voltage protection (ovp) threshold voltage 3.0 to 4.4 6.2 6.5 6.9 v r on charging fet on resistance ( 12 , 13 ) 3.0 to 4.4 v bus_in =4.2 v-5.0 v, i on =1 a 200 m? i ocp over-current protection (ocp) threshold current 3.0 to 4.4 v bus_in =5.2 v 1.20 1.65 a continued on the following page
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 13 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus switch path dc electrical characteristics (continued) all typical values are at t a =25c unless otherwise specified. symbol parameter v bat (v) v bus (v) condition t a = -40 to +85c unit min. typ. max. audio_r / audio_l switch on paths r on audio switch on resistance ( 12 , 13 ) 3.0 to 4.4 v l/r =-0.8 v, 0.8 v; i on =30 ma ; f=0 -470 khz 3. 5 ? v l/r =-1.5 v, 1.5 v ; i on =30 ma, f=0 -470 khz 4.0 r flat audio r on flatness ( 12 , 14 ) 3.0 to 4.4 v l/r =-0.8 v, 0.8 v; i on =30 ma, f=0 -470 khz 0.1 ? v l/r =-1.5 v, 1.5 v; i on =30 ma, f=0 -470 khz 0.2 r term internal termination resistors 1 .5 k? mic switch on paths r on mic path on resistance ( 12 , 13 ) 3.0 to 4.4 mic connected to v bus_in , v sw =0, 2.8 v; i on =30 ma 40 ? mic connected to dp_con, v sw =0, 2.8 v; i on =30 ma 40 mic ovp over-voltage protection (ovp) threshold voltage with mic on v bus_in ( 15 ) mic connected to v bus_in entering ovp 2.80 3.35 v total current consumption ( 17 ) i bat battery supply standby mode current no accessory attached (id_con floating) 3.0 to 4.4 floating vbus floating 10 15 a average battery supply standby mode current with accessory attached (id_con not floating) 0 .0 id_dis=1 35 50 5 .0 id_dis=1 100 ( 16 ) 150 ( 16 ) notes: 11. does not apply to the chg_detb pin because it is open drain. 12. limits based on electrical characterization data. 13. on resistance is the voltage drop between the two terminals at the indicated current through the switch. 14. flatness is the difference between the maximum and minimum val ues of on resistance over the specified range of conditions. 15. the mic bias applied should not exceed 2.8 v. 16. v ddio of either 0 v or in the valid range of 1.7 v to 3.6 v. 17. typically the battery charg es from v bus .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 14 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 15. capacitance symbol parameter v bat (v) condition t a = -40 to +85c unit min. typ. max. c on usb dp_con , d m_con on capacitance (usb mode, both host1 and host2) 3.8 v bias =0.2 v , f=1 mhz 8 pf c i capacitance for each i/o p in 3.8 2 pf c off off capacitance (host1 and host2) 3.8 2 pf 16. i 2 c ac electrical characteristics symbol parameter fast mode min. max. unit f scl scl clock frequency 0 400 khz t hd;sta hold time (repeated) start condition 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su;sta set- up time for repeated start condition 0.6 s t hd;dat data hold time 0 0.9 s t su;dat data set-up time ( 18 ) 100 ns t r rise time of sda and scl signals ( 19 ) 20+0.1c b ( 18 ) 300 ns t f fall time of sda and scl signals ( 19 ) 20+0.1c b ( 18 ) 300 ns t su;sto set-up time for stop condition 0.6 s t buf bus-free time between stop and start conditions 1.3 s t sp pulse width of spikes that must b e suppressed by the input filter 0 50 ns notes: 18. c b equals the total capacitance of one bus line in pf. if mixed with high-speed devices; faster fall times are allowed, accordin g to the i 2 c bus specification. 19. a fast-mode i 2 c b us ? device can be used in a standard-mode i 2 c-bus system, but the requirement that t su;dat 250 ns must be met. this is automatically the case if the device does no t stretch the low period of the scl signal. if a device does stretch the low period of the scl signal, it must output the next data bit to th e sda line t r_max + t su;dat = 1000 + 250 = 1250 ns before the scl line is released (according to the standard-mode i 2 c bus specification). figure 6. definition of timing for full-speed mode devices on the i 2 c b us ? table 5. i 2 c slave address name size (bits) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 slave address 8 0 1 0 0 1 0 1 r/w
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 15 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 17. switch path ac electrical characteristics all typical values are for v bat =3.8 v at t a =25oc unless otherwise specified. symbol parameter conditions t a = -40 to +85c unit min. typ. max. xtalk active channel crosstalk dp_con to dm_con audio mode f=20 khz, r t = 32 ?, c l =0 pf - 90 db u sb mode f =1 mh z, r t = 50 ?, c l =0 pf - 60 o irr off isolation audio mode f= 20 khz, r t = 32 ?, c l =0 pf - 100 db u sb mode f=1 mhz, r t = 50 ?, c l =0 pf - 60 psrr power supply rejection ratio , mic on v bus_in power supply noise 300 mv pp , f=217 hz sine wave - 10 0 db thd total harmonic distortion (audio path) 20 hz to 20 khz, r l =32/16 ?, input signal range -1 .5 v, +1 .5 v 0.07 % t sk(p) skew of opposite transitions of the same output (usb mode) t r =t f =750 ps (10-90%) at 240 mhz, c l =0 pf, r l =50 ? 35 ps t i2crst time when i2c_sda and i2c_scl both low to cause reset see figure 7 30 ms t sdpdet time from v bus_in valid to v bus_out valid with charger fet closed and usb switches cl osed for usb standard downstream port see figure 9 12 0 ms t chgout time from v bus_in valid to v bus_out valid with charger fet closed for both usb charging ports (cdp and dcp) see figure 10 160 ms t carkit time from v bus_in valid to car kit type-1 or type- 2 charger detected see figure 11 140 ms t iddet time from id_con not floating to intb low to signal accessory attached that is id_con resistance-based only (v bus_in not v alid , default timing configuration) see figure 12 150 ms t bc11 timeout for data contact during dcd check 300 600 900 ms
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 16 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 18. timing diagrams v bat i2c_sda internal reset time 30ms 30ms 400us 400us standby mode figure 7. i 2 c reset mode timing figure 8. int mask to intb interrupt timing diagram 120ms 120ms vbus_in vbus_out usb switch state charger fet closed usb switches closed vbus >4.0v xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx float float id resistance closed open figure 9. usb standard downstream port attach timing ( 20 ) vbat vddio int_mask intb int mask clear int event int mask written via i 2 c command int read
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 17 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus v bus voltage v bus_out charger fet closed, usb switches closed, and intb and chg_detb asserted v bus >4.0v xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx float float id resistance charger detection time 160ms intb pin chg_detb pin usb switch state 160ms closed open figure 10. usb dedicated charging port (dcp) or charging downstream port (cdp) attach timing ( 20 ) v bus voltage v bus >4.0v id resistance xxxxxxxx float v bus_out 140ms intb pin vbus detection time 140ms chg_detb pin usb switch state charger fet closed, usb switches closed, and intb and chg_detb asserted closed open bb configures switches closed figure 11. car kit type-1 and type-2 attach timing 150ms usb switch state intb asserted accessory attached id resistance xxxxxx float intb pin bb reads intb bb configures switches closed closed open bb read and clear figure 12. id -based accessories, no v bus_in attach timing ( 21 ) notes: 20. usb switch state timing is based on automatic switching mode (en_man_sw = 0 ) . a utomatic switching excludes dcp. 21. id_con resistance detection based on default timing set and applicati ons register values and on initial id_con accessory attach only (50 ms resistor detection time with three id checks on in itial attach = 150 ms typical detection time).
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 18 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 19. bit definitions table 6. i 2 c register map address register type reset value bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h device id r 00010000 version id do not use 02h control r/w 11010001 dcd timeout en resetb id _dis en_man_sw do not use do not use do not use int mask 03h interrupt r/c 00000000 do not use ocp change ovp change mic_ovp change resistor code change v bus _valid change bc1.2_complete do not use 05h interrupt mask r/w 00000000 do not use ocp ovp mic_ovp resistor code change v bus _valid bc1.2_complete do not use 07h resistor code r 00000000 do not use do not use do not use resistor code 08h timing set r/w 00000000 do not use resistor detection time 09h status r 00000000 id_short ocp ovp mic_ovp /id_float v bus _valid bc1.2_active dcd 0ah device type r 00000000 do not use do not use dock do not use do not use usb dedicated charging port (dcp) usb charging downstream port (cdp) usb standard downstream port (sdp) 0bh dac sar r 00000000 dac sar value 13h manual sw r/w 00100111 d- switching d+ switching v bus switching 14h manual chg_ctrl r/w 00000000 do not use do not use do not use assert chg_detb mic_ovp_en assert_d+ do not use 1bh applications1 r/w x 00 010 00 do not use do not use do not use # of consecutive id matches for attach do not use do not use 1ch applications2 r/w xxxx0101 do not use do not use do not use do not use # id checks for resistor code change max. capacitance on id table 7. device id ? address: 01h ? reset value: 0001 0000 ? type: read bit # name size (bits) description 7:3 version id 5 rev 0.0=00010 2:0 do not use 3 do not use table 8. control ? address: 02h ? reset value: 11010001 ? type: read/write bit # name size (bits) description 7 dcdtimeout_en 1 1: dcd timeout is enabled. 0: dcd timeout is disabled. 6 resetb 1 1: do nothing. 0: reset fsa9285a C resets all of fsa9285a except the control register (02h) , manual sw (13h), and manual chg_ctrl(14h). note : this bit is momentarily set to 0 on a write. it immediately re verts to 1. 5 id _dis 1 1: id_con resistor detection is disabled after a resistance is detec ted on id_con. 0: id_con resistor detection is enabled after a resistance is detecte d on id_con. note : the fsa9285a continues to monitor for an id_float condition. 4 en_man_sw 1 1: configure switches based on manual sw register settings.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 19 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus bit # name size (bits) description 0: use only defined automatic switch settings. this bit needs to be cleared in case of a weak battery explicitly or the device must be defaulted via a v ddio reset for the dead battery case to operate properly. 3 do not use 1 do n ot u se . 2 do not use 1 do not u se . 1 do not use 1 do not u se . 0 int mask 1 1: mask interrupt C do not interrupt baseband processor when a bit is set in the interrupt register. 0: unmask interrupt C interrupt baseband processor if any bit is set in the interrupt register. table 9. interrupt ? address: 03h ? reset value: 00000000 ? type: read/clear bit # name size (bits) description 7 do not use 1 n/a 6 ocp c hange 1 1: ocp state change d. 0: ocp state has not changed. 5 ovp c hange 1 1: ovp state change d. 0: ovp state has not changed. 4 mic_ovp change 1 1: mic ovp state change d. 0: mic ovp state not changed. 3 resistor code change 1 1: resistor code value change d. 0: resistor code value has not changed. note : this interrupt is disabled when id_dis=1. the fsa9285a interrupts if t ransitioning from a non-zero resistor code to a resistor code=zero (id_con floating). 2 v bus _valid change 1 1: v bus _valid state change d. 0: v bus _valid state has not changed. 1 bc1.2_complete 1 1: bc1.2 charger detection complete. 0: no change in bc1.2 charger detection status. 0 do not use 1 n/a table 10. interrupt mask ? address: 05h ? reset value: 00000000 ? type: read/write bit # name size (bits) description 7 do not use 1 n/a 6 ocp 1 1: mask ocp state-change interrupt. 0: do not mask ocp state-change interrupt. 5 ovp 1 1: mask ovp state-change interrupt. 0: do not mask ovp state-change interrupt. 4 mic_ovp 1 1: mask mic_ovp state-change interrupt. 0: do not mask mic_ovp state-change interrupt.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 20 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus bit # name size (bits) description 3 resistor code change 1 1: mask resistor code value-change interrupt. 0: do not mask resistor code value-change interrupt. 2 v bus _valid 1 1: mask v bus _ valid state-change interrupt. 0: do not mask v bus_valid state-change interrupt. 1 bc 1.2_complete 1 1: mask bc1 .2 _complete interrupt. 0: do not mask bc1.2_complete interrupt. 0 do not use 1 n/a table 11. resistor code ? address: 07h ? reset value: 00000000 ? type: read bit # name size (bits) description 7:5 do not use 3 n/a 4:0 resistor code 5 resistor code value read from id_con (s ee table 3 resistor identification). table 12. timing set ? address: 08h ? reset value: 00000000 ? type: read/write bit # name size (bits) description 7:4 do not use 4 n/a 3:0 resistor detection time 4 time to complete the id_con resistance measurement for accesso ry detection (see table 13). table 13. timing table for timing set register setting value resistor detection time (ms) 0000 50 0001 100 0010 150 0011 200 0100 300 0101 400 0110 500 0111 600 1000 700 1001 800 1010 900 1011 1000 1100 1101 -1111
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 21 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus table 14. status ? address: 09h ? reset value: 00000000 ? type: read/write bit # name size (bits) description 7 id_short 1 1: id_short detected. 0: id_short not detected. 6 ocp 1 1: v bus in over-current state. 0: v bus not in over-current state. 5 ovp 1 1: v bus in over-voltage state. 0: v bus not in over-voltage state. 4 mic_ovp 1 1: mic in over-voltage state 0: mic not in over-voltage state 3 /id_float 1 1: id_con not floating (resistor detected). 0: id_con floating (no resistor detected). 2 v bus _valid 1 1: v bus is valid. 0: v bus is not valid. 1 bc 1.2_active 1 1: bc 1.2 is active. (this is true if a connect is attempted with dcd timeout disabled and no dcd.) 0: bc1.2 idle. 0 dcd 1 1: data contact detected on last charger-detect sequence. 0: no data contact detected on last charger-detect sequence. table 15. device type ? address: 0ah ? reset value: 00000000 ? type: read bit # name size (bits) description 7 do not use 1 do not u se . 6 do not use 1 do not u se . 5 dock 1 1: charging dock detected. 0: charging dock not detected. 4 do not use 1 do not u se . 3 do not use 1 do not u se . 2 dcp 1 1: usb dedicated charging port (dcp) charger detected. 0: usb dedicated charging port (dcp) charger not detected. 1 cdp 1 1: usb charging downstream port (cdp) charger detected. 0: usb charging downstream port (cdp) charger not detected. 0 sdp 1 1: usb standard downstream port (sdp) detected. 0: usb standard downstream port (sdp) not detected.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 22 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus table 16. dac sar ? address: 0bh ? reset value: 00000000 ? type: read bit # name size (bits) description 7:0 dac_sar 8 dac_sar value C indicates raw 8-bit resistance value detected (see table 3 resistor identification). table 17. manual sw ( 22 ) ? address: 13h ? reset value: 00100111 ? type: read/write bit # name size (bits) description 7:5 dm_con switching 3 000: open all switches. 001: dm_con connected to dm_host1 of usb port. 010: dm_con connected to audio_l. 011: dm_con connected to dm_host2 of usb port. 4:2 dp_con switching 3 000: open all switches. 001: dp_con connected to dp_host1 of usb port. 010: dp_con connected to audio_r. 011: dp_con connected to dp_host2 of usb port. 100: dp_con connected to mic. 1:0 v bus_in switching 2 00: open all switches. 01: do not u se . 10: v bus_in connected to mic. 11: v bus_in connected to v bus_out (phone sinks current from attached accessory). ( 23 ) notes: 22. when changing manual switch configurations on a single attach, the accesso ry must pass through an open all switches state between configurations. manual modes require the en_man_sw manual mode bit in the control register (02h) to be set. 23. v bus_in must be valid for the charger fet to close in manual fet switching . table 18. manual chg_ctrl ? address: 14h ? reset value: 00000000 ? type: read/write bit # name size (bits) description 7:5 do not use 3 n/a 4 assert chg_detb 1 1: assert chg_detb low. 0: normal operation (chg_detb asserted low for dcp, cdp, aca, and car kit type 1/2; chg_detb is high otherwise.) note : en_man_sw is not required for this bit to take effect. 3 mic_ovp_en 1 1: enable mic_ovp (only use when mic is connected to v bus ). 0: do not enable mic_ovp. note : en_man_sw is not required for this bit to take effect. 2 assert_d+ 1 1: force 0.6 v on dp_con. 0: do not force 0.6 v on dp_con. note : en_man_sw is not required for this bit to take effect, v bus must be valid. 1:0 do not use 2 n/a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 23 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus table 19. applications1 ? address: 1b h ? reset value: x 00010 00 ? type: read/write bit # name size (bits) description 7:5 do not use 3 n/a 4 :2 # consecutive id matches for attach 3 000: 1 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 1 :0 do not use 2 n/a table 20. applications2 ? address: 1ch ? reset value: xxxx0101 ? type: read/write bit # name size (bits) description 7:4 do not use 4 n/a 3:2 # id checks for resistor code change 2 00: 1 01: 2 10: 3 11: 4 1:0 max. capacitance on id 2 00: 500 pf 01: 1 nf 10: 1.5 nf 11: 2 nf
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 24 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 20. reference schematic vbus_out dp_con id_con dm_con gnd vbus_in intb i2c_sda i2c_scl dp_host2 dm_host2 audio_r audio_l dp_host1 dm_host1 pmic ap or baseband mic vddio vbat 1.8 ~ 3.6v micro usb connector 1f 1f 1f 2.2 ? 2.2 ? 2.2 ? chg_detb v ddio baseband or charger ic optional (leave open if not used) 10k ? 1.2~ 10k ? 1.2~ 10k ? v ddio txd rxd d+ d- audio codec 1f gpio sda scl mic bias 1pf tvs 1pf tvs 1pf tvs tvs battery v br 32v r on 1.4 ? id tv_out figure 13. reference schematic
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fsa9285a ? rev. 1.3 25 fsa9285a mcpc compliant usb port multimedia switch with auto-detection, 12 v v bus 21. layout guidelines pcb layout guidelines for high-speed usb signal integrity 1. place the fsa9285a as close to the usb controller as possible. shorter traces mean less loss, less chanc e of picking up stray noise, and less radiated emi. a) keep the distance between the usb controller and the device less than 25.4 mm (or one inch <1 in). b) for best results, keep this distance <18 mm. this keeps it less than one quarter (?) of the transmission electrical length. 2. use an impedance calculator to ensure 90 ? differential impedance for dp_com/dm_con lines. 3. select the best transmission line for the application. a) for example, for a densely populated board, select an edge -coupled differential stripline. 4. minimize the use of vias and keep hs usb lines on same plane in the stack. a) vias are an interruption in the impedance of the transmission line and should be avoided. b) try to avoid routing schemes that generally force the use of at least two vias: one on each end to get the signal to and from the surface. 5. cross lines, only if necessary, orthogonally to avoid noise coupling (traces running in parallel couple). 6. if possible, separate hs usb lines with gnd to improve isolation. a) avoid routing gnd, power, or components close to the transmission lines to avoid impedance discontinuities. 7. match transmission line pairs as much as possible to improve skew performance. 8. avoid sharp bends in pcb traces; a chamfer or rounding is generally preferred. 9. place decoupling for power pins as close to the device as possible. a) use low-esr capacitors for decoupling if possible. b) if needed, a tuned pi filter should be used to negate the effects of switching power supplies and other noise sources. layout for global system for mobile communication (gsm) time division multiple channel (tdma) buzz reduction there are two possible mechanisms for tdma/gsm noise to negatively impact fsa9285a devices performance. the first is the result of large current draw by the phone transmitter during active signaling when the transmitter is at full or almost f ull power. with the phone transmitter dumping large amounts of current in the phone gnd plane; it is possible for there to be temporary voltage excursions in the gnd plane if not properly designed. this noise can be coupled back up through the gnd plane into the fsa9285a device and, although the fsa9285a has very good isolation; if the gnd noise amplitude is la rge enough, it can result in noise coupling to the vbus_in / mic pin. the second path for gsm noise is through electromagnetic coupling onto the signal lines themselves. ordering information part number operating temperature range top mark package FSA9285AUCX -40 to +85c nq 20 -lead, wlcsp (2.010 x 1.672 x 0.625 mm , 0.4 mm pitch) product-specific package dimensions product d e x y fsa9285a ucx 2.010 mm 1.672 mm 0.2 36 mm 0.2 05 mm
bottom view side views top view ball a1 index area 1 2 3 4 a b c d e seating plane 20x a1 c 0.005 c a b f ?? e d b a 0.6250.547 0.06 c 0.05 c e d f ? ? notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asmey14.5m, 2009. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 586 microns ?0,&52160,&5216 f. for dimensions d, e, x, and y see product datasheet. g. drawing filname: mkt-uc020aarev4. 0.03 c 2x 0.03 c 2x 0.40 1.20 0.40 1.60 <? ;? recommended land pattern (nsmd type) ?cu pad ?6roghu mask opening 0.40 1.20 0.40 1.60 a1 ? cu pad ?6roghu mask opening 0.40 1.20 option 1 option 2
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